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[Category : - Computers and computer accessories - ELECTRICITY & LIGHTING- Telecommunications]
[Viewed 1946 times]

This circuit of synchronous counter is for 4-bit only. However, it can be extended further for any number of bits in the similar fashion. It contains very less number of gates as compared to counter using JK F/Fs. This leads to low power consumption and low cost. Also, the number of stages is only two in each counting unit if edge pulse detector circuit is not considered .

Without further elaboration, the foregoing will so fully illustrate my invention, that others may, by applying current of future knowledge, readily adapt the same for use under various conditions of service. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention.

Advantages over the prior art
The synchronous counter circuit proposed by the present invention has the following advantages over the prior art:
a) This circuit needs less number of transistors,
b) It needs low power consumption and less area,
b) It is speed efficient,
b) This circuit is cost effective,
c) It is economical in maintenances

Financial information

The patent for this invention is pending. Its application number is 1144/KOL/2013.
It has been presented here for sale.
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