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Fabricate High-Performance Passive Components on SILICON ICs

[Category : - Telecommunications]
[Viewed 1640 times]

A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by a method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.

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A Planar Dielectric Platform has the potential to deliver the following improved performance features from SILICON integrated circuits:

1. Higher performance from passive components (e.g. inductors with high Qs)
2. Lower power consumption
3. Lower operating temperature
4. Lower noise
5. Smaller die size
6. Lighter weight
7. Lower cost
8. Increased reliability

Patent publications:

US 6307247

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addinc (United States)

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