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Negative Latency DSP for High Performance FPGA Control Loops

[Category : - ELECTRONICS]
[Viewed 114 times]

The invention provides a robust negative latency Digital Signal Processing (DSP) method which when combined with a simple additional signal allows for complex signal processing without the unwanted effects of delays due to ADC conversion time, Controller/Filter computation time and DAC reconstruction time etc.
This arrangement is ideally suited to signal processing realized by DSP and FPGA devices.

The novelty and performance of the arrangement has been previously validated and published in collaboration with Professor Clarke F.R.S, University of Oxford, England.

The arrangement has been proven in both a commercial product and an updated experimental development utilizing a low-cost floating-point FPGA.

New and emerging floating-point FPGA devices mean that the zero-latency signal processing capability can now be applied to extremely high-frequency closed-loop applications which have traditionally been limited by unwanted and unavoidable time delays.









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