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FREQUENCY AND PHASE LOCKED LOOPS

[Category : - DESIGN PATENTS- Computers and computer accessories - Telecommunications]
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I submitted a phase-locked loop (PLL) patent application.

The patent application analysis of the root causes of jitter problems, from design theory to the specific design of phase-locked loop, and proposed a new solution to significantly remove most jitter (long-term jitter, cycle-by-cycle jitter, etc.). The lock-up time can be decreased from 10 ms to a level of about 10 microseconds, and it ensures high static frequency and phase accuracy (better than 50ppm).

The structure of the present invention with conventional phase-locked loop is essentially different.

The pending patent application content is published in November 2014 by EDN.

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Any electronic device operating at high frequency > 1GHz needs Phase locked Loop

such as cellphone or computer.

Jihai Zhang
Inventor / Owner
Email: [Use the button below to contact me], [Use the button below to contact me]

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